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features ? fast read access time - 120 ns ? automatic page write operation ? internal address and data latches for 128-bytes ? internal control timer ? fast write cycle time ? page write cycle time - 10 ms maximum ? 1 to 128-byte page write operation ? low power dissipation ? 80 ma active current ? 300 a cmos standby current ? hardware and software data protection ? d a t a polling for end of write detection ? high reliability cmos technology ? endurance: 10 4 or 10 5 cycles ? data retention: 10 years ? single 5v 10% supply ? cmos and ttl compatible inputs and outputs ? jedec approved byte-wide pinout pin configuration pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect 0010f?peepr?02/10 at28c010 mil 1-megabit (128k x 8) paged parallel eeproms at28c010 military cerdip, flatpack top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 pga top view 44 lcc top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 a12 a7 a6 a5 nc nc nc a4 a3 a2 a1 a13 a8 a9 a11 nc nc nc nc oe a10 ce 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 a0 i/o0 i/o1 i/o2 vss nc i/o3 i/o4 i/o5 i/o6 i/o7 a15 a16 nc nc nc nc vcc we nc nc a14 32 lcc top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 nc vcc we nc (continued)
2 0010f?peepr?02/10 at28c010 military description the at28c010 is a high-performance electrically erasable and programmable read only mem- ory. its one megabit of memory is organized as 131,072 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 120 ns with power dissipation of just 440 mw. when the device is deselected, the cmos standby current is less than 300 a. the at28c010 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 128-byte page register to allow writing of up to 128- bytes simultaneously. during a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by d a t a polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmel's 28c010 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention character- istics. an optional software data protection mechanism is available to guard against inadvertent writes. the device also includes an extra 128-bytes of eeprom for device identification or tracking. block diagram absolute maximum ratings* temperature under bias ............................... -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v
3 0010f?peepr?02/10 at28c010 military device operation read: the at28c010 is accessed like a static ram. when c e and o e are low and w eis high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either c eor o e is high. this dual-line control gives designers flexibility in preventing bus contention in their system. byte write: a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. once a byte write has been started it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a polling operation. page write: the page write operation of the at28c010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. a page write operation is ini- tiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. each successive byte must be written within 150 s(t blc ) of the previous byte. if the t blc limit is exceeded the at28c010 will cease accepting data and commence the internal programming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a7 - a16 inputs. for each w e high to low transition during the page write operation, a7 - a16 must be the same. the a0 to a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. d a t a polling: the at28c010 features d a t a polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the com- plement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit: in addition to data polling the at28c010 provides another method for determin- ing the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection: if precautions are not taken, inadvertent writes may occur during transi- tions of the host system power supply. atmel has incorporated both hardware and software fea- tures that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the at28c010 in the following ways: (a) v cc sense - if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power-on delay - once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of o elow, c e high or w e high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. software data protection: a software controlled data protection feature has been implemented on the at28c010. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28c010 is shipped from atmel with sdp disabled. sdp is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algo- rithm). after writing the 3-byte command sequence and after t wc the entire at28c010 will be protected against inadvertent write operations. it should be noted, that once protected the host may still perform a byte or page write to the at28c010. this is done by preceding the data to be written by the same 3-byte command sequence used to enable sdp.
4 0010f?peepr?02/10 at28c010 military once set, sdp will remain active unless the disable command sequence is issued. power transi- tions do not disable sdp and sdp will protect the at28c010 during power-up and power-down conditions. all command sequences must conform to the page write timing specifications. the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write opera- tion. after setting sdp, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be polling operations. device identification: an extra 128-bytes of eeprom memory are available to the user for device identification. by raising a9 to 12v 0.5v and using address locations 1ff80h to 1ffffh the bytes may be written to or read from in the same manner as the regular memory array. optional chip erase mode: the entire device can be erased using a 6-byte software code. please see software chip erase application note for details. notes: 1. x can be vil or vih. 2. refer to ac programming waveforms dc and ac operating range at28c010-12 at28c010-15 at28c010-20 at28c010-25 operating temperature (case) mil. -55c - 125c -55c - 125c -55c - 125c -55c - 125c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z dc characteristics symbol parameter condition min max units i li input load current v in =0vtov cc +1v 10 a i lo output leakage current v i/o =0vtov cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v 300 a i sb2 v cc standby current ttl ce = 2.0v to v cc +1v 3 ma i cc v cc active current f = 5 mhz; i out =0ma 80 ma v il input low voltage 0.8 v
5 0010f?peepr?02/10 at28c010 military ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc -t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce -t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact in t acc . 3. t df is specified from oe or ce wichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 5. if ce is de-asserted, it must remain de-asserted for at least 50ns during read operations other- wise incorrect data may be read. v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage cmos i oh = -100 a; v cc = 4.5v 4,2 v dc characteristics (continued) symbol parameter condition min max units ac read characteristics symbol parameter at28c010-12 at28c010-15 at28c010-20 at28c010-25 units min max min max min max min max t acc address to output delay 120 150 200 250 ns t ce (1) ce to output delay 120 150 200 250 ns t oe (2) oe to output delay 0 50 0 55 0 55 0 55 ns t df (3, 4) ce or oe to output float 0 50 0 55 0 55 0 55 ns t oh output hold from oe, ce or address, whichever occurred first 0000ns t ceph (5) ce pulse high time 50 50 50 50 ns
6 0010f?peepr?02/10 at28c010 military input test waveforms and measurement level output test load note: 1. this parameter is 100% characterized and is not 100% tested. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 410pfv in =0v c out 812pfv out =0v ac write characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 s t wph write pulse width high 50 ns
7 0010f?peepr?02/10 at28c010 military ac write waveforms we controlled ce controlled page mode characteristics symbol parameter min max units t as ,t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 100 ns t ds data set-up time 50 ns t dh ,t oeh data, oe hold time 0 ns
8 0010f?peepr?02/10 at28c010 military page mode write waveforms (1)(2) notes: 1. a7 through a16 must specify the page address during each high to low transition of we (or ce). 2. oe must be high only when we and ce are both low.
9 0010f?peepr?02/10 at28c010 military chip erase waveforms software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data if loaded. 4. 1 to 128 bytes of data are loaded. t s = 5 msec (min.) t w =t h = 10 msec (min.) v h = 12.0v 0.5v load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2)
10 0010f?peepr?02/10 at28c010 military software data protection disable algorithm (1) software protected program cycle waveform (1)(2)(3) notes: 1. a0 - a14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7 - a16) must be the same for each high to low transition of we (or ce). 3. oe must be high only when we and ce are both low. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa exit data protect state (3)
11 0010f?peepr?02/10 at28c010 military notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any addres location may be used but the address should not vary. data polling characterstics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
12 0010f?peepr?02/10 at28c010 military note: 1. see valid part number table below. at28c010 ordering information (1) t acc (ns) i cc (ma) ordering code package operation range active standby 120 80 0.3 at28c010(e)-12dm/883 at28c010(e)-12em/883 at28c010-12fm/883 at28c010(e)-12lm/883 at28c010(e)-12um/883 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) 150 80 0.3 at28c010(e)-15dm/883 at28c010(e)-15em/883 at28c010-15fm/883 at28c010(e)-15lm/883 at28c010(e)-15um/883 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) 200 80 0.3 at28c010-20dm/883 at28c010-20em/883 at28c010-20fm/883 at28c010-20lm/883 at28c010-20um/883 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) 250 80 0.3 at28c010-25dm/883 at28c010-25em/883 at28c010-25fm/883 at28c010-25lm/883 at28c010-25um/883 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) package type 32d6 32-lead, 0.600" wide, non-windowed, ceramic dual inline (cerdip) 32f 32-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 32l 32-pad, non-windowed, ceramic leadless chip carrier (lcc) 44l 44-pad, non-windowed, ceramic leadless chip carrier (lcc) 30u 30-pin, ceramic pin grid array (pga) w die options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles
13 0010f?peepr?02/10 at28c010 military note: 1. see valid part number table below. 5962-38267 ordering information (1) t acc (ns) i cc (ma) ordering code package operation range active standby 120 80 0.3 5962-38267 07 mxx 5962-38267 07 mux 5962-38267 07 mzx 5962-38267 07 myx 5962-38267 07 mtx 32d6 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) 150 80 0.3 5962-38267 05 mxx 5962-38267 05 mux 5962-38267 05 mzx 5962-38267 05 myx 5962-38267 05 mtx 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) 200 80 0.3 5962-38267 03 mxx 5962-38267 03 mux 5962-38267 03 mzx 5962-38267 03 myx 5962-38267 03 mtx 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) 250 80 0.3 5962-38267 01 mxx 5962-38267 01 mux 5962-38267 01 mzx 5962-38267 01 myx 5962-38267 01 mtx 32d6 32l 32f 44l 30u military/883c class b, fully compliant (-55 cto125 c) package type 32d6 32-lead, 0.600" wide, non-windowed, ceramic dual inline (cerdip) 32f 32-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 32l 32-pad, non-windowed, ceramic leadless chip carrier (lcc) 44l 44-pad, non-windowed, ceramic leadless chip carrier (lcc) 30u 30-pin, ceramic pin grid array (pga) w die
14 0010f?peepr?02/10 at28c010 military valid part numbers the following table lists standard atmel products that can be ordered. options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles device numbers speed package and temperature combinations at28c010 12 dm/883, em/883, fm/883, lm/883, um/883 at28c010e 12 dm/883, em/883, lm/883, um/883 at28c010 15 dm/883, em/883, fm/883, lm/883, um/883 at28c010e 15 dm/883, em/883, lm/883, um/883 at28c010 20 dm/883, em/883, fm/883, lm/883, um/883 at28c010 25 dm/883, em/883, fm/883, lm/883, um/883 at28c010 ?w die products reference section: parallel eeprom die products
at28c010 mil 15 packaging information 0010f?peepr?02/10 11.63(0.458) 11.23(0.442) 14.22(0.560) 13.72(0.540) 2.54(0.100) 2.16(0.085) 1.91(0.075) 1.40(0.055) index corner 0.635(0.025) 0.381(0.015) x 45 0.305(0.012) 0.178(0.007) radius 0.737(0.029) 0.533(0.021) 1.02(0.040) x 45 pin 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 2.16(0.085) 1.65(0.065) 7.62(0.300) bsc 1.27(0.050) typ 10.16(0.400) bsc 16.81(0.662) 16.26(0.640) 16.81(0.662) 16.26(0.640) 2.74(0.108) 2.16(0.085) 2.03(0.080) 1.40(0.055) index corner 0.635(0.025) 0.381(0.015) x 45 0.305(0.012) 0.178(0.007) radius 0.737(0.029) 0.533(0.021) 1.02(0.040) x 45 pin 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 2.16(0.085) 1.65(0.065) 12.70(0.500) bsc 1.27(0.050) typ 12.70(0.500) bsc pin #1 id 9.40(0.370) 6.86(0.270) 0.51(0.020) 0.38(0.015) 1.27(0.050) bsc 1.14(0.045) max 3.05(0.120) 2.49(0.098) 1.14(0.045) 0.66(0.026) 1.83(0.072) 0.76(0.030) 10.36(0.408) 9.02(0.355) 0.18(0.007) 0.10(0.004) 12.40(0.488) 11.99(0.472) 21.08(0.830) 20.60(0.811) 42.70(1.68) 41.70(1.64) pin 1 15.50(0.610) 13.00(0.510) 2.49(0.098)max 0.127(0.005)min 1.52(0.060) 0.38(0.015) 0.58(0.023) 0.36(0.014) 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 17.80(0.700) max 0.381(0.015) 0.203(0.008) 2.54(0.100)bsc 5.08(0.200) 3.18(0.125) seating plane 5.72(0.225) max 38.10(1.500) ref 0o~ 15o ref mil-std-1835 c-12 44l , 44-pad, non-windowed, ceramic leadless chip carrier (lcc) dimensions in inches and (millimeters)* jedec outline mo-115 32l , 32-pad, non-windowed, ceramic leadless chip carrier (lcc) dimensions in inches and (millimeters)* 32d6 , 32-lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) dimensions in inches and (millimeters) mil-std-1835 d-16 config a 32f , 32-lead, non-windowed, ceramic bottom brazed flat package (flatpack) dimensions in inches and (millimeters) mil-std-1835 f-18 config b *controlling dimension: millimeters *controlling dimension: millimeters
at28c010 mil 16 packaging information 0010f?peepr?02/10 13.74(0.541) 13.36(0.526) 16.18(0.637) 15.82(0.623) 2.57(0.101) 2.06(0.081) 7.26(0.286) 6.50(0.256) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 12.70(0.500) typ 2.54(0.100) typ 16.71(0.658) 16.31(0.642) 2.54(0.100) typ 10.41(0.410) 9.91(0.390) 30u , 30-pin, ceramic pin grid array (pga) dimensions in inches and (millimeters)
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